AT6000 FPGAs Application Note

Convolution is one of the basic and most common operations in both analog and digital domain signal processing. Often times, it is desirable to modulate a given signal in order to enhance or extract important information contained in it. This signal modulation is generally known as filtering. In two-dimensional digital signal processing (2-D DSP), a 3 x 3 convolver is commonly used in applications such as object detection and feature extraction of 2-D images. However, due to the compute-intensive nature (multiply-add operations) of 2-D convolution, the size of the required digital logic circuitry increases accordingly. In this application note, we present an efficient single-chip FPGA implementation of a bit-parallel 3 x 3 symmetric convolver that features run-time software-configurable convolver coefficients (taps). Our reference design takes full advantage of time-division multiplexing (TDM), pipelining, CacheLogic, and vector multiplication. We will also discuss an alternative to using CacheLogic, which features run-time hardware selfconfigurable LUT using static random access memory (SRAM).